Michael J. Wirthlin Associate Professor Department of Electrical and…

Michael J. Wirthlin

Associate Professor
Department of Electrical and Computer Engineering                  TEL: (801) 422-7601
Brigham Young University                                           FAX: (801) 422-0201
459 Clyde Building                                                 Email: wirthlin@ee.byu.edu
Provo, UT 84602                                                    http://www.byu.edu/faculty/wirthlin

Education:
Ph.D.   Brigham Young University, Provo, UT - Electrical and Computer Engineering
        Dissertation: Improving Functional Density Through Run-Time Circuit Reconfiguration
        August 1997
B.S.    Brigham Young University, Provo, UT - Electrical and Computer Engineering
        August 1992, Suma Cum Laude with University Honors
        Honors Thesis: A Quantitative Study of RISC Pipelining Techniques Using Custom Software Simulation Tools

Areas of Specialization:
        High-Level Synthesis                                  FPGA Reliability
        Reconfigurable Computing Architectures                Digital Circuit Design
        Application-Specific Computing Architectures          FPGA Circuit Design
        Electronic Design Automation (EDA)                    Reliable Computing

Professional Experience:
Associate Professor (1999 ­ present)
Dept. of Electrical and Computer Engineering, Brigham Young University, Provo, UT
    · Graduate and undergraduate teaching in Computer Engineering and Digital Design
    · Research in configurable computing architectures, application-specific computing, application-specific synthesis
         approaches, FPGA reliability, application-specific signal processing architectures, and configurable system on chip

Staff Engineer (1997-1998)
National Semiconductor, Architecture Laboratory, Santa Clara, CA
    · Investigate and develop system design methodologies for single-chip systems
    · Create system performance modeling for embedded system on chip architectures

Design Engineer (1992-1994)
National Technology Incorporated, Salt Lake City, UT
    · FPGA design of digital sound products
    · Configurable computing architecture development

Controls Engineer, Co-Op (1990-1991)
Saturn Corporation, Lost Foam and Vehicle Systems Operations, Spring Hill, TN
    · PLC programmer for automobile manufacturing facility

Professional Activities

Senior Member of the IEEE, member of IEEE Computer Society
Member of the Association for Computing Machinery (ACM), Tau Beta Pi
Reviewer for IEEE Transactions on VLSI Systems, Kluwer Journal of VLSI Signal Processing, IEEE
   Computer Magazine, ACM Design Automation Conference, IEEE Symposium on Field-
   Programmable Custom Computing Machines, IEEE Transactions on Computers, and the
   International Symposium on Signal Processing and its Applications (ISSPA).
Technical program committee for ACM/SIGDA International Symposium on Field-Programmable Gate
   Arrays, International conference on Engineering of Reconfigurable Systems and Algorithms, and
   International Conference on Military and Aerospace Programmable Logic Devices (MAPLD).
Special session organizer (Reconfigurable System on Chip Architectures), International conference on
   Engineering of Reconfigurable Systems and Algorithms (2004)
Member of ACM/SIGDA DAC PhD forum organizing committee (2002-2004)
Department graduate coordinator

Courses Taught:

     ECEN 220/224s: Introductory Digital Design and State Machines
     ECEN 320: Advanced Digital Design
     ECEN 427: Embedded Systems
     ECEN 490: Senior Project (Computer System Design Project, FPGA Software Radio Project)
     ECEN 528: Advanced Computer Architecture
     ECEN 625: Synthesis and Optimization of Digital Circuits

Courses Developed:

     Advanced Digital Design Course: Developed a new five credit hour junior level digital design
     course to include relevant topics and more advanced material.

     Advanced Digital Design Laboratory: Initiated the use of FPGAs in undergraduate teaching
     laboratories. Organized laboratory sequence for students to design and test a simple 16-bit processor.

     Synthesis and Optimization of Digital Circuits: Introduced a new graduate course on digital
     circuit synthesis with an emphasis on scheduling and resource sharing.

     Computer Systems Senior Project: Introduced a new senior project involving the specification,
     design, and testing of a complete computer system (hardware and software). Students taking this
     class participated in the IEEE Computer Society International Design Competition (CSIDC) and
     placed 3rd in the 2001 finals in Washington D.C.


Publications:

Journal Publications

1.   Welson Sun, Michael J. Wirthlin, and Stephen Neuendorffer, "FPGA Pipeline Synthesis Design Exploration Using
     Module Selection and Resource Sharing", IEEE Transactions on Computer Aided Design, Vol. 26, No. 2, pp. 254-265,
     February 2007.

2.   Maya Gokhale, Paul Graham, Michael Wirthlin, D. Eric Johnson, and Nathaniel Rollins, "Dynamic Reconfiguration for
     Management of Radiation-Induced Faults in FPGAs", International Journal of Embedded Systems, Vol. 2, No. 1/2, pp.
     28-38, 2006.
3.   Keith Morgan, Michael Caffrey, Paul Graham, Eric Johnson, Brian Pratt, and Michael Wirthlin, "SEU-Induced
     Persistent Error Propagation in FPGAs", IEEE Transactions on Nuclear Science, Vol. 52, No. 6, Part 1, pp. 2438 -
     2445, December 2005.

4.   D. Eric Johnson, Michael Caffrey, Paul Graham, Nathan Rollins, and Michael Wirthlin, "Accelerator Validation of an
     FPGA SEU Simulator", IEEE Transactions on Nuclear Science, Vol. 50, No. 6, pp. 2147-2157, December 2003.

5.   Paul Graham, Michael Caffrey, D. Eric Johnson, Nathan Rollins, and Michael Wirthlin, "SEU Mitigation for Half-
     Latches in Xilinx Virtex FPGAs", IEEE Transactions on Nuclear Science, Vol. 50, No. 6, pp. 2139-2146, December
     2003.

6.   Michael J. Wirthlin, "Constant Coefficient Multiplication Using Look-up Tables", Journal of VLSI Signal Processing,
     Vol. 36, pp. 7-15, 2004.

7.   Edward A. Lee, Stephen Neuendorffer, and Michael J. Wirthlin, "Actor-Oriented Design of Embedded Hardware and
     Software Systems", Invited paper to the Journal of Circuits, Systems, and Computer, Vol. 12, No. 3, pp. 231-260, June
     2003.

8.   Michael J. Wirthlin and Brian McMurtrey, "Web-Based IP Evaluation and Distribution Using Applets", IEEE
     Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 22, No. 8, pp. 985-994, August
     2003.

9.   B. L. Hutchings, B. Nelson and M. J. Wirthlin, "Designing and Debugging Custom Computing Applications", IEEE
     Design and Test of Computers, Vol. 17, No. 1, pp. 20-28, January 2000.

10. M. J. Wirthlin and B.L. Hutchings, "Improving Functional Density Using Run-Time Circuit Reconfiguration", IEEE
    Transactions on VLSI Systems, vol. 6, no. 2, pp. 247-256, 1998.


Conference Publications
11. Matthew French, Paul Graham, Michael Wirthlin, and Li Wang, "Cross Functional Design Tools for Radiation
    Mitigation and Power Optimization of FPGA Circuits", Earth Science Technology Conference, NASA, Washington
    D.C., June 2006.

12. Michael J. Wirthlin and Welson Sun, "DSynth: A Pipeline Synthesis Environment for FPGAs", IEEE Symposium on
    Field-Programmable Custom Computing Machines (short paper), pp. 343-344. April 2006.

13. Matthew French, Li Wang, and Michael Wirthlin, "Power Visualization, Analysis, and Optimization Tools for
    FPGAs", IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 185-191. April 2006.

14. Brian Pratt, Michael Caffrey, Paul Graham, Keith Morgan, and Michael Wirthlin, "Improving FPGA Design
    Robustness with Partial TMR", IEEE International Reliability Physics Symposium (IRPS), pp. 226-232, April 2006.

15. Welson Sun, Michael J. Wirthlin, and Stephen Neuendorffer, "Combining Module Selection and Resource Sharing for
    Efficient FPGA Pipeline Synthesis", 2006 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
    (FPGA 2006), pp. 179-188, February 2006.

16. Brian Pratt, D. Eric Johnson, Michael J. Wirthlin, Michael Caffrey, Keith Morgan, and Paul Graham, "Improving
    FPGA Design Robustness with Partial TMR", 8th Annual International Conference on Military and Aerospace
    Programmable Logic Devices (MAPLD), September 2005.

17. Michael J. Wirthlin, "Senior-Level Embedded Systems Design Project Using FPGAs", Proceedings of the 2005 IEEE
    International Conference on Microelectronic Systems Education (MSE '05), pp. 91-92, June 2005.
18. Matthew French, Paul Graham , Michael Wirthlin, Li Wang, Gregory Larchev, "Radiation Mitigation and Power
    Optimization Design Tools for Reconfigurable Hardware in Orbit", Earth Science Technology Conference, NASA,
    Washington D.C., June 2005.

19. Nathan Rollins, Michael J. Wirthlin, Michael Caffrey, and Paul S. Graham, "Evaluation of Power Costs in Applying
    TMR to FPGA Designs", 7th Annual International Conference on Military and Aerospace Programmable Logic Devices
    (MAPLD), Washington D.C., 2004, Paper P136.

20. D. Eric Johnson, Keith S. Morgan, Michael J. Wirthlin, Michael Caffrey, and Paul S. Graham, "Persistent Errors in
    SRAM-based FPGAs", 7th Annual International Conference on Military and Aerospace Programmable Logic Devices
    (MAPLD), Washington D.C., 2004, Paper P135.

21. Maya Gokhale, Paul Graham, Eric Johnson, Nathan Rollins, and Michael Wirthlin, "Dynamic Reconfiguration for
    Management of Radiation-Induced Faults in FPGAs", 11th Annual Reconfigurable Architectures Workshop (RAW
    2004), Sante Fe, NM, 2004. pp. 145 - 152, ISBN 0-7695-2132-0.

22. M. French, P. Graham, and M. Wirthlin, "Design Tools for Reconfigurable Hardware in Orbit", NASA Earth Science
    Technology Conference 2004, Palo Alto, CA, June 22-24. ISBN 0-9721439-6-3.

23. Michael J. Wirthlin, "Computer Systems Design Competition at BYU", 2003 Frontiers in Education, IEEE Education
    Society, pp. F1F-15 ­ F1F-21, November 2003.

24. Nathan Rollins, Michael Wirthlin, Paul Graham, and Michael Caffrey, "Evaluating TMR Techniques in the Presence of
    Single Event Upsets", 6th Annual International Conference on Military and Aerospace Programmable Logic Devices
    (MAPLD), Paper P63 September 2003.

25. Michael J. Wirthlin, Nathan Rollins, Michael Caffrey, and Paul Graham, "Hardness by design techniques for field-
    programmable gate arrays", Proceedings of the 11th Annual NASA Symposium on VLSI Design, Coeur d'Alene, ID, pp.
    WA11.1-WA11.6, May 2003.

26. Michael J. Wirthlin, Eric Johnson, Nathan Rollins, Michael Caffrey, and Paul Graham , "The Reliability of FPGA
    Circuit Designs in the Presence of Radiation Induced Configuration Upsets", Proceedings of the 2003 IEEE
    Symposium on Field-Programmable Custom Computing Machines, pp. 133-142. April 2003.

27. Paul Graham, Michael Caffrey, Michael Wirthlin, Eric Johnson, and Nathan Rollins, "Reconfigurable Computing in
    Space: From Current Technology to Reconfigurable Systems-On-a-Chip", 24th Annual IEEE Aerospace Conference,
    Vol. 5, pp. 5:2399-5:2410, March 2003.

28. Nathan Rollins, Michael J. Wirthlin, Michael Caffrey, and Paul Graham, "Reliability of Programmable Input/Output
    Pins in the Presence of Configuration Upsets", 5th Annual International Conference on Military and Aerospace
    Programmable Logic Devices (MAPLD), Paper C3, September 2002.

29. Michael Caffrey, Paul Graham, Eric Johnson, and Michael Wirthlin, "Single-Event Upsets in SRAM FPGAs", 5th
    Annual International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), Paper P8,
    September 2002.

30. W. Landaker and M. J. Wirthlin, "Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System", 12th
    International Conference on Field Programmable Logic and Applications (FPL-2002), pp. 806-815, August 2002.

31. M.J. Wirthlin and B. McMurtrey, "IP Delivery for FPGAs Using Applets and JHDL", Proceedings of the 39th Design
    Automation Conference (DAC), pp. 2-7, June 2002.

32. E. Johnson, M. J. Wirthlin, and M. Caffrey, "Single-Event Upset Simulation on an FPGA", International Conference
    on Engineering of Reconfigurable Systems and Algorithms (ERSA 2002), pp. 68-73, June 2002.
33. M. J. Wirthlin and B. McMurtrey, "Efficient Constant Coefficient Multiplication Using Advanced FPGA
    Architectures", Proceedings of the 11th International Workshop on Field-Programmable Logic and Applications
    (FPL), pp 555-564, August 2001.

34. M. J. Wirthlin, B. L. Hutchings and C. Worth, "Synthesizing Hardware from Java Byte Codes", Proceedings of the
    11th International Workshop on Field-Programmable Logic and Applications (FPL), pp 123-132, August 2001.

35. M. J. Wirthlin and N. Sundaramoorthy, "Measuring the Routing Costs of FPGA Circuit Components". Proceedings of
    the International Conference on Parallel and Distributed Processing Techniques and Applications, Volume I, pp 129-
    134, June 2000.

36. M. J. Wirthlin, S. Morrison, P. Graham and B. Bray, "Improving Performance and Efficiency of an Adaptive
    Amplification Operation Using Configurable Hardware", Proceedings of the IEEE Workshop on FPGAs for Custom
    Computing Machines, pp. 267-275, April 2000.

37. M. J. Wirthlin and B.L. Hutchings, "Improving Functional Density Through Run-Time Constant Propagation", 1997
    ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 86-92, February 1997.

38. M.J. Wirthlin and B.L. Hutchings, "Sequencing Run-Time Reconfigured Hardware with Software", 1996 ACM/SIGDA
    International Symposium on Field Programmable Gate Arrays, pp. 122-128, February 1996.

39. M.J. Wirthlin and B.L. Hutchings, "A Dynamic Instruction Set Computer", Proceedings of the IEEE Workshop on
    FPGAs for Custom Computing Machines, pp. 99 - 107, April 1995.

40. M.J. Wirthlin and B.L. Hutchings, "DISC: The Dynamic Instruction Set Computer", Field Programmable Gate Arrays
    (FPGAs) for Fast Board Development and Reconfigurable Computing, John Schewel, Editor, Proc. SPIE 2607, pp. 92-
    103 (1995).

41. B.L. Hutchings and M.J. Wirthlin, "Implementation Approaches for Reconfigurable Logic Applications", 5th
    International Workshop on Field Programmable Logic and Applications, pp 419-428, August 1995.

42. M.J. Wirthlin, K.L. Gilson, and B.L. Hutchings, "The Nano Processor: A Low Resource Reconfigurable Processor",
    Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 23-30, April 1994.

Patents
43. Michael J. Wirthlin and Brad L. Hutchings, "Dynamically-Configurable Digital Processor Using Method for
    Relocating Logic Array Modules", U.S. Patent Number 6,173,434, January 2001.

Presentations and Posters
44. Joshua D. Engel, Keith S. Morgan, and Michael J. WirthlinPoster: "A Methodology for Estimating On-orbit Static
    Single Event Upset Rates Using CREME96", 9th Annual International Conference on Military and Aerospace
    Programmable Logic Devices (MAPLD), September 2006.

45. Matthew French, Michael Wirthlin, and Paul Graham, Poster: "Reducing Power Consumption of Radiation Mitigated
    Designs for FPGAs", 9th Annual International Conference on Military and Aerospace Programmable Logic Devices
    (MAPLD), September 2006.

46. Nathan Rollins and Michael J. Wirthlin, Poster: "Reducing Energy in FPGA Multipliers Through Glitch Reduction",
    8th Annual International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), September
    2005.
47. Matthew French, Li Wang, Tyler Anderson, and Michael J. Wirthlin, Poster: "Integrated Tool Suite for Post Synthesis
    FPGA Power Consumption Analysis", 8th Annual International Conference on Military and Aerospace Programmable
    Logic Devices (MAPLD), September 2005.

48. Michael J. Wirthlin, invited presentation, "Reliable Spatial Computing", 1st Annual Distributed Embedded Computing
    Conference, Sante Fe, NM, June 2005.

49. Michael J. Wirthlin, Invited Tutorial, "Evaluating Soft Errors in FPGAs", IEEE International Reliability Physics
    Symposium, April 2004.

50. Paul Graham, Michael Caffrey, Michael Wirthlin, D. Eric Johnson, and Nathan Rollins, Poster: "SEU Mitigation for
    Half-Latches in Xilinx Virtex FPGAs", 2003 IEEE Nuclear and Space Radiation Effects Conference, June 2003.

51. Michael Wirthlin, D. Eric Johnson, Nathan Rollins, Paul Graham, and Michael Caffrey, Poster: "Validation of an
    FPGA Fault Simulator ", 2003 IEEE Nuclear and Space Radiation Effects Conference, June 2003.

52. Michael J. Wirthlin, Trent Vandenberghe, and Devin Pratt , "JHDL Domain", presentation at the 5th Bi-annual Ptolemy
    mini-conference, University of California at Berkeley, May 2003.

53. Michael J. Wirthlin, and Matthew Koecher , "JHDL Hardware Generation", presentation at the 5th Bi-annual Ptolemy
    mini-conference, University of California at Berkeley, May 2003.

54. Michael J. Wirthlin, "The Effects of Upsets within the Configuration Memory of SRAM FPGAs", presentation at the
    IEEE Microelectronics Reliability and Qualification Workshop, December 2002.

55. Michael J. Wirthlin, Eric Johnson, and Michael Caffrey, "Single-Event Upset Simulation for Field Programmable Gate
    Arrays", presentation at the 2002 IEEE Nuclear and Space Radiation Effects Conference (NSREC 2002), 2002.

56. Michael J. Wirthlin, "Integrating the JHDL Design Environment into Ptolemy-II", presentation at the 4th Bi-annual
    Ptolemy mini-conference, University of California, March 2001.

Externally Funded Contracts:

National Science Foundation
        PI: Brent Nelson, Co-PI: Mike Wirthlin, 1/07-12/07, $10,000
        "Brigham Young University To Join the I/UCRC CHREC Center"

Los Alamos National Laboratory, U.S. Department of Energy
        PI: Michael Wirthlin, 1/07-12/09, $300,000
        "Automated Design Techniques for Improving FPGA Fault Tolerance"

Lockheed Marting CE&T
        PI: Michael Wirthlin, 9/06-9/07, $50,000
        "Dynamic Internal Reconfigurable Technology"

Los Alamos National Laboratory, U.S. Department of Energy
        PI: Michael Wirthlin, 1/06-9/06, $50,000
        "Reliability Modeling of the Xilinx VirtexII and Virtex4 FPGAs"

Los Alamos National Laboratory, U.S. Department of Energy
        PI: Michael Wirthlin, 1/04-12/06, $270,000
        "Improving the Reliability of FPGA Designs through Automated Design Hardening"

Xilinx Corporation
         PI: Brent Neslon, Co-PI: Michael Wirthlin, 4/04-4/05, $80,000
        "Pro-Media Processor Development Kit"

National Aeronautics and Space Administration (NASA), sub-contract through USC-ISI
        Sub-contract PI: Michael Wirthlin, 5/03-4/06, $150,000
        "Reconfigurable Hardware IN Orbit (RHINO)"

Los Alamos National Laboratory, U.S. Department of Energy
        PI: Michael Wirthlin, 1/02-12/03, $120,000
        "Improving the Reliability of FPGA Designs Operating in a Space Environment"

Defense Advanced Research Projects Agency
        PI: B. Hutchings, Co-PI: B. Nelson, M. Wirthlin, and D. Wilde, 1999-2002, $2,489,870
        "Unified Debug Environment for Adaptive Computing Systems"


Internally Funded Projects:
Ira Fulton College of Engineering and Technology, Brigham Young University
         M. Wirthlin, 2005, $6,500
         "Optimized Retiming and Operation Selection for Reconfigurable Data-Path Architectures"

Watson Embedded Systems Laboratory, Dept. of Electrical and Computer Engineering
        M. Wirthlin, 2004-2005, $12,000
        "High-Level Scheduling and Mapping Techniques for Reconfigurable Datapaths"

College of Engineering and Technology, Brigham Young University
        M. Wirthlin, 2000, $5,400
        "Exploratory Research in Temporal Partitioning and Scheduling"

Student Graduates:
Dan L. McMurtrey, Masters of Science, December 2006
        "Using duplication with compare for on-line error detection in FPGA-based designs"

Keith S. Morgan, Masters of Science, August 2006
         "SEU-Induced Persistent Error Propagation in FPGAs"

D. Eric Johnson, Masters of Science, August 2005
         "Estimating the Dynamic Sensitive Cross Section of FPGA Design Through Fault Injection"

Matthew R. Koecher, Masters of Science, December 2003
       "Hardware Synthesis of Synchronous Data Flow Models"

Brian J. McMurtrey, Masters of Science, April 2003
         "Approaches in Web Based Design and Evaluation of Digital Circuits"

Benjamin L. Bullough, Masters of Science, August 2002
       "Analysis of Field-Programmable Gate Array Implementations of Constant Coefficient Finite Impulse Response
       Filters"

Wesley J. Landaker, Masters of Science, August 2002
        "Using Hardware Context-Switching to Enable a Multitasking Reconfigurable Computer System"

Steven E. Morrison, Masters of Science, April 2001
"Design and Performance Analysis of a Configurable Hardware Solution of an Adaptive Automatic Target
Recognition Algorithm"