Third Call for Papers…

                                                 Third Call for Papers
   IEEE Asian Solid-State Circuits Conference (A-SSCC) 2008
                        Location: JAL Resort Sea Hawk Hotel, Fukuoka, Japan
                  Date: November 3, 2008 (Monday) ­ November 5, 2008 (Wednesday)
                                          Sponsored by IEEE SSCS, IEEE Region-10 SSCS Chapters
The IEEE A-SSCC 2008 (Asian Solid-State Circuits Conference) is an international forum for presenting the most updated and advanced chips and circuit
designs in solid-state semiconductor fields. The conference is supported by the IEEE Solid-State Circuits Society and is held in Asia every year. Further
details on the conference and paper submission guidelines and templates are available at the A-SSCC official website http://a-sscc.org/.

Paper Submission
Prospective authors are invited to submit full-length, four-page manuscripts, including figures, tables and references, to the official
A-SSCC 2008 website. All papers will be handled and reviewed electronically. Papers are solicited in the following categories:

Regular Sessions
1. Analog Circuits & Systems: Amplifiers, comparators, switch capacitor circuits, continuous-time & discrete-time filters, voltage/current
   references; DC-DC converters, power-control circuits, linear regulators; IF/baseband analog circuits, AGC/VGA; display driver circuits;
   non-linear analog circuits.
2. Data Converters: Nyquist-rate and oversampling A/D and D/A converters, sub-circuits for data converters including sample-and-hold circuits,
   calibration circuits.
3. Digital Circuits & Systems: Design, fabrication, and test of digital VLSI systems; High-speed low-power digital circuits, power-reduction and
   management methods for digital VLSI, leakage reduction techniques; clock distribution, I/O circuits, reconfigurable logic-array circuits; supply
   /substrate noise measurement and cancellation for digital VLSI, variation and fault-tolerant circuits.
4. SoC & Signal Processing Systems: System-on-chip, microprocessors, network processors, baseband communication processing system &
   architectures, low-power signal-processing systems; multimedia processors including video, image, audio and voice processing systems;
   cryptographic- and security-processing circuits and systems; bio-medical/neural signal processors.
5. RF: Receivers/transmitters/transceivers for wireless systems; narrowband RF, ultra-wideband and millimeter-wave circuits (MMDS, 60GHz);
   Circuits and sub-circuits for RF front-end, LNA, mixer, power amplifiers, VCOs, frequency synthesizers, RF filters, RF switches, power detectors,
   active antennas.
6. Wireline & Mixed-Signal Circuits: Receivers/transmitters/transceivers for wireline systems including (but not limited to) LAN, WAN, FDDI,
   Ethernet, token-ring, fiber channel, SONET, SDH, PON, ATM, ISDN, xDSL, cable-modem; optical/electrical data links and backplane
   transceivers; power-line communication; Clock generation circuits, PLL, DLL, spread-spectrum clock generation.
7. Emerging Technologies and Applications: Advanced circuit technologies and techniques; ultra-low-voltage and sub-threshold logic design;
   molecular-, organic-, and nano-electronics; flexible substrates and printable electronics; 3D-integration and novel packaging technologies;
   compound-semiconductor, superconductive, and micro-photonic technologies and circuits; energy sources and energy harvesting; biomedical and
   ambient-intelligence; emerging wireless applications and circuits; RFID; analog and optical processors, non-transistor-based analog and digital
   circuits and systems; advanced memory technologies; spintronics; and quantum storage.
8. Memory: Static, dynamic, non-volatile, and read-only memory; magnetic and ferro-electric memory designs and architectures; data storage and
   multi-bit-cell-based memory designs; embedded memory architectures, cache-memory systems, multi-port memory, and CAM designs,
   nano-crystal, phase-change, and 3D memories; yield-enhancement redundancy and ECC techniques; and memory testing and built-in self-test.

Special Sessions
1. Industry Program: This special category accepts only papers based on state-of-the-art products. The paper may cover specifications,
   applications, state-of-the-art points, chip photos, chip architecture/software, circuits (not necessarily very original, significant improvement is
   fine), live demo if any, characterization results, and packaging/testing results.
2. Student Design Contest: A student design contest is held among the accepted papers with system prototypes or measurement results of which
   operations can be demonstrated on-site. Refer to the web for further information.

Papers on low-power and/or low-voltage approaches, signal integrity, noise, test, and manufacturability for all the above categories are welcomed.
Measurement results are highly recommended, especially for analog, and RF categories. Design methodologies for SiP, SoC, interconnections and
statistical design are included in the scope of the conference; the papers only describing CAD tools and CAD algorithms are not considered. Dual
submission to other conferences is not allowed. A special issue of the IEEE Journal of Solid-State Circuits will be prepared for publication of the
outstanding papers of this conference.

Important dates
June 9, 2008, 20:00 (GMT)                      Paper submission deadline (Extended)
July 25, 2008                                  Acceptance notification
August 29, 2008                                Deadline for final papers submission

Steering Committee    Chair                              Chorng-Kuang Wang, National Taiwan University, Taiwan
                      Co-Chair                           Takayasu Sakurai, University of Tokyo, Japan
Conference Chair                                         Katsuhiro Shimohigashi, STARC, Japan
             Co-Chair                                    Ming-Kai Tsai, Mediatek Corp., Taiwan
             Organizing Committee Chair                  Koji Kito, STARC, Japan
             Organizing Committee Co-Chair               Yoshinobu Adachi, STARC, Japan
Technical Program Committee  Chair                       Hoi-Jun Yoo, KAIST, Korea
                             Co-Chair                    Tohru Furuyama, Toshiba Corp., Japan
                             Vice-Chair                  SeongHwan Cho, KAIST, Korea